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page 1 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * samsung electronics reserves the right to ch ange products or specification without notice. 1gb c-die ddr3 sdram specification revision 1.0 june 2007
page 2 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c revision history revision month year history 0.0 january 2007 - revision 0.0 release 0.1 june 2007 - deleted 800mbps 5-5-5 speed - timing parameters by speed grade (13.0) - input/output capacitance (11.0) 1.0 june 2007 - revision 1.0 specification release.
page 3 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c 1.0 ordering information ...................................................................................................... ..............................................4 2.0 key features .............................................................................................................. ...................................................4 3.0 package pinout/mechanical dime nsion & addressing .......................................................................... ...................5 3.1 x4 package pinout (top view) : 94ball fbga package(78balls + 16 balls of support balls) ..........................................5 3.2 x8 package pinout (top view) : 94ball fbga package(78balls + 16 balls of support balls) ..........................................6 3.3 x16 package pinout (top view) : 112ball fbga package(96balls + 16 balls of support balls) ......................................7 3.4 fbga package dimension (x4) ............................................................................................................................... ....8 3.5 fbga package dimension (x8) .............................................................................................................................. .....9 3.6 fbga package dimension (x16) .............................................................................................................................. .10 4.0 input/output functional description ................. ...................................................................... .................................11 5.0 ddr3 sdram addressing ..................................................................................................... ....................................12 6.0 absolute maximum ratings .. ................................................................................................ .....................................14 6.1 absolute maximum dc ratings ............................................................................................................................... .14 6.2 dram component operating temperature range ....................................................................................................14 7.0 ac & dc operating conditions ...................... ........................................................................ ...................................14 7.1 recommended dc operating conditions (sstl_1.5) .................................................................................................14 8.0 ac & dc input measurement levels .............. ............................................................................ ...............................15 8.1 ac and dc logic inpu t levels for single-ended signals .............................................................................................15 8.2 differential swing requirement for differntial signals ................................................................................................16 8.2.1 single-ended requirements for differential signals ............................................................................................17 8.3 ac and dc logic in put levels for diffe rential signals .................................................................................................18 8.4 differential input cross point voltage .......................................................................................................................18 8.5 slew rate definition for single ended input signals ...................................................................................................19 8.5.1 input slew rate for inpu t setup time (tis) and data setup time (tds) ...............................................................19 8.5.2 input slew rate for inpu t hold time (tih) and data hold time (tdh) ..................................................................19 8.6 slew rate definition for differential input signals ......................................................................................................19 9.0 ac and dc output measurement levels ........................................................................................ .......................... 20 9.1 single ended ac and dc output levels ....................................................................................................................20 9.2 differential ac and dc output levels .......................................................................................................................20 9.3.single ended output slew rate ............................................................................................................................... . 21 9.4 differential output slew rate .............................................................................................................................. ......21 9.5 reference load for ac timing and output slew rate ................................................................................................22 9.6 overshoot/undershoot specification ........................................................................................................................23 9.6.1 address and control overshoot and undershoot specifications .......................................................................23 9.6.2 clock, data, strobe an d mask overshoot and undershoot specifications ..........................................................23 9.7 34 ohm output dr iver dc electrical characteristics ..................................................................................................24 9.7.1 output drive temperature and voltage sensitivity ............................................................................................25 9.8 on-die termination (odt) levels and i-v characteristics ..........................................................................................25 9.8.1 odt dc electrical characteristics .....................................................................................................................26 9.8.2 odt temperature and voltage sensitivity ......................................................................................................... 27 9.9 odt timing definitions ............................................................................................................................... ............. 28 9.9.1 test load for odt timings ............................................................................................................................... 28 9.9.2 odt timing definition .............................................................................................................................. ........28 10.0 idd specification pa rameters and test conditions ......................................................................... ......................31 10.1 idd measurement conditions .............................................................................................................................. ...31 10.2 idd specifications .............................................................................................................................. ....................41 11.0 input/output capaci tance ............. ................ ................ ............. ............. ............. ............. .......................................43 12.0 electrical characterist ics and ac timing for ddr3-800 to ddr3-1600 ....................................................... .........44 12.1 clock specification ............................................................................................................................... ..................44 12.2 clock jitter specification .............................................................................................................................. ..........45 12.3 refresh parameters by device density ...................................................................................................................46 12.4 standard speed bins ............................................................................................................................... ...............46 13.0 timing parameters by spee d grade .......................................................................................... ............................. 48 table contents
page 4 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c ? jedec standard 1.5v 0.075v power supply ? vddq = 1.5v 0.075v ? 400 mhz f ck for 800mb/sec/pin, 533mhz f ck for 1066mb/sec/pin, 667mhz f ck for 1333mb/sec/pin ? 8 banks ? posted cas ? programmable cas latency: 5, 6, 7, 8, 9, 10, (11 for high density only) ? programmable additive latency: 0, cl-2 or cl-1 clock ? programmable cas write latency (cwl) = 5 (ddr3-800), 6 (ddr3-1066), 7 (ddr3-1333) ? 8-bit pre-fetch ? burst length: 8 (interleave without any limit, sequential with starting address ?000? only), 4 with tccd = 4 which does not allow seamless read or write [either on the fly using a12 or mrs] ? bi-directional differential data-strobe ? internal(self) calibration : internal self calibration through zq pin (rzq : 240 ohm 1%) ? on die termination using odt pin ? average refresh period 7.8us at lower than t case 85c, 3.9us at 85c < t case < 95 c ? asynchronous reset ? package : 94 balls fbga - x4/x8 (with 16 support balls) 112 balls fbga - x16 (with 16 support balls) ? all of lead-free products are compliant for rohs the 1gb ddr3 sdram c-die is or ganized as a 32mbit x 4/16mbit x 8/ 8mbit x 16 i/os x 8banks device. this synchronous device achieves high speed double-data-rate transfer rates of up to 1333mb/sec/pin (ddr3- 1333) for general applications. the chip is designed to comply with the following key ddr3 sdram fea- tures such as posted cas, programmable cwl, internal (self) calibra- tion, on die termination using odt pin and asynchronous reset . all of the control and address inputs ar e synchronized with a pair of exter- nally supplied differential clocks. inputs are latched at the crosspoint of dif- ferential clocks (ck rising and ck falling). all i/os are synchronized with a pair of bidirectional strobes (dqs and dqs ) in a source synchronous fash- ion. the address bus is used to convey row, column, and bank address information in a ras /cas multiplexing style. the ddr3 device operates with a single 1.5v 0.075v power supply and 1.5v 0.075v vddq. the 1gb ddr3 device is available in 94ball fbgas(x4/x8) and 112ball fbga(x16) note : 1. the functionality described an d the timing specifications included in this data sheet are for the dll enabled mode of operation. 2. 1066mbps cl7 doesn?t have back-ward compatibility with 800mbps cl5 note : this data sheet is an abstract of full ddr3 specification and does not cover the common features which are described in ?ddr3 sdram device operation & timing diagram?. [ table 1 ] samsung ddr3 ordering information table note : 1. speed bin is in order of cl-trcd-trp. 2. x4/x8/x16 package - including 16 support balls organization ddr3-800 (6-6-6) ddr3-1066 (7-7-7/8-8-8) ddr3-1333 (8-8-8/9-9-9) package 256mx4 k4b1g0446c-zcf7 k4b1g0446c-cf8/g8 k4b1g0446c-zcg9/h9 94 fbga 128mx8 k4b1g0846c-zcf7 k4b1g0846c-cf8/g8 k4b1g0846c-zcg9/h9 94 fbga 64mx16 k4b1g1646c-zcf7 k4b1g1646c-c f8/g8 K4B1G1646C-ZCG9/h9 112 fbga [ table 2 ] 1gb ddr3 c-die speed bins speed ddr3-800 ddr3-1066 ddr3-1333 unit 6-6-6 7-7-7 8-8-8 8-8-8 9-9-9 tck(min) 2.5 1.875 1.5 ns cas latency 6 7 8 8 9tck trcd(min) 15 13.125 15 12 13.5 ns trp(min) 15 13.125 15 12 13.5 ns tras(min) 37.5 37.5 37.5 36 36 ns trc(min) 52.5 50.625 52.5 48 49.5 ns 1.0 ordering information 2.0 key features
page 5 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c 3.1 x4 package pinout (top view) : 94ball fbga package (78balls + 16 balls of support balls) 3.0 package pinout/mechani cal dimension & addressing 1 2 3 4 5 6 7 8 9 10 11 a nc nc nc nc nc nc b c d nc vss vdd nc nc vss vdd nc d e vss vssq dq0 dm vssq vddq e f vddq dq2 dqs dq1 dq3 vssq f g vssq nc dqs vdd vss vssq g h vrefdq vddq nc nc nc vddq h j nc vss ras ck vss nc j k odt vdd cas ck vdd cke k l nc cs we a10/ap zq nc l m vss ba0 ba2 a15 vrefca vss m n vdd a3 a0 a12/bc ba1 vdd n p vss a5 a2 a1 a4 vss p r vdd a7 a9 a11 a6 vdd r t nc vss reset a13 nc a8 vss nc t u v w nc nc nc nc nc nc note1: a1,a2,a4,a8,a10,a11,d1,d11,t1,t11,w1,w2,w4,w8,w10 and w11 balls indicate mechanical support balls with no internal conne ction populated ball ball not populated ball locations (x4) top view (see the balls through the package) 1234 89 567 a b c d e f g h j k l n m 10 11 p r t u v w
page 6 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c 1 2 3 4 5 6 7 8 9 10 11 a nc nc nc nc nc nc b c d nc vss vdd nc nu/tdqs vss vdd nc d e vss vssq dq0 dm/tdqs vssq vddq e f vddq dq2 dqs dq1 dq3 vssq f g vssq dq6 dqs vdd vss vssq g h vrefdq vddq dq4 dq7 dq5 vddq h j nc vss ras ck vss nc j k odt vdd cas ck vdd cke k l nc cs we a10/ap zq nc l m vss ba0 ba2 nc vrefca vss m n vdd a3 a0 a12/bc ba1 vdd n p vss a5 a2 a1 a4 vss p r vdd a7 a9 a11 a6 vdd r t nc vss reset a13 nc a8 vss nc t u v w nc nc nc nc nc nc note1: a1,a2,a4,a8,a10,a11,d1,d11,t1,t11,w1,w2,w4,w8,w10 and w11 balls indicate mechanical support balls with no internal conne ction populated ball ball not populated ball locations (x8) top view (see the balls through the package) 1234 89 567 a b c d e f g h j k l n m 10 11 p r t u v w 3.2 x8 package pinout (top view) : 94ball fbga package (78balls + 16 balls of support balls)
page 7 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c 1 2 3 4 5 6 7 8 9 10 11 a nc nc nc nc nc nc b c d nc vddq dqu5 dqu7 dqu4 vddq vss nc d e vssq vdd vss dqsu dqu6 vssq e f vddq dqu3 dqu1 dqsu dqu2 vddq f g vssq vddq dmu dqu0 vssq vdd g h vss vssq dql0 dml vssq vddq h j vddq dql2 dqsl dql1 dql3 vssq j k vssq dql6 dqsl vdd vss vssq k l vrefdq vddq dql4 dql7 dql5 vddq l m nc vss ras ck vss nc m n odt vdd cas ck vdd cke n p nc cs we a10/ap zq nc p r vss ba0 ba2 a15 vrefca vss r t vdd a3 a0 a12/bc ba1 vdd t u vss a5 a2 a1 a4 vss u v vdd a7 a9 a11 a6 vdd v w nc vss reset a13 nc a8 vss nc w y aa ab nc nc nc nc nc nc note1: a1,a2,a4,a8,a10,a11,d1,d11,w1,w11,ab1,ab2,ab4,ab8,ab10 and ab11 balls indicate mechanical support balls with no internal connection populated ball ball not populated ball locations (x16) top view (see the balls through the package) 1234 89 567 a b c d e f g h j k l n m 10 11 p r t u v w y aa ab 3.3 x16 package pinout (top view) : 112ball fbga package (96balls + 16 balls of support balls)
page 8 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c a b c d e f g h m n p r t 11.00 0.10 0.80 x 18 = 14.40 0.80 x 10 = 8.00 4.00 0.80 7.20 94 - ? 0.45 solder ball 0.2 ab m (datum b) (datum a) 0.10max 0.50 0.05 1.10 0.10 #a1 10 87654321 11 9 1.60 11.00 0.10 18.00 0.10 molding area u v w 0.35 0.05 #a1 index mark b a bottom view top view 3.4 fbga package dimension (x4) 18.00 0.10 j k l 0.80 0.80
page 9 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c a b c d e f g h j l m n p r t 11.00 0.10 4.00 0.80 7.20 94 - ? 0.45 solder ball 0.2 ab m (datum b) (datum a) 0.10max 0.50 0.05 1.10 0.10 #a1 10 87654321 11 9 1.60 11.00 0.10 18.00 0.10 molding area u v w 0.35 0.05 #a1 index mark bottom view top view 3.5 fbga package dimension (x8) 18.00 0.10 k 0.80 0.80 0.80 x 18 = 14.40 0.80 x 10 = 8.00 b a
page 10 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c a b c d e f g h j k l m n p r t 11.00 0.10 0.80 x 21 = 16.80 0.80 x 10 = 8.00 8.40 112 - ? 0.45 solder ball 0.2 ab m (datum b) (datum a) 10 87654321 11 9 molding area u v w #a1 index mark y aa ab bottom view 3.6 fbga package dimension (x16) 18.00 0.10 0.10max 0.50 0.05 1.10 0.10 #a1 11.00 0.10 18.00 0.10 0.35 0.05 top view 0.40 0.80 4.00 0.80 1.60 b a
page 11 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 3 ] input/output function description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and c ontrol input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck cke input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is as ynchronous for self refresh exit. after vrefca has become stable during the power on and initialization sequence, it must be maintained during all operations (including self- refresh). cke must be maintained high throughout r ead and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power-down. input buffers , excluding cke, are disabled during self -refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on systems with multiple ranks. cs is considered part of the command code. odt input on die termination: odt (registered high) enables termination resi stance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, dqs and dm/tdqs, nu/tdqs (when tdqs is enabled via mode register a11=1 in mr1) signal for x8 configurations. the odt pin will be ignor ed if the mode register (mr1) is pro- grammed to disable odt. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm (dmu), (dml) input input data mask: dm is an input mask signal for write data. input da ta is masked when dm is sampled high coinci- dent with that input data during a write access. dm is sa mpled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs is enabled by mode register a11 setting in mr1. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs cycle. a0 - a12 input address inputs: provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (a10/ap and a12/bc have additional functions, see below) the address inputs also provide the op-code during mode register set commands. a10 / ap input autoprecharge: a10 is sampled during read/write commands to determine whether autoprecharge should be per- formed to the accessed bank after the read/write operation. (high:autoprecharge; low: no autoprecharge) a10 is sampled during a precharge command to determi ne whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by bank addresses. a12 / bc input burst chop: a12 is sampled during read and write commands to determine if burst chop(on-the-fly) will be per- formed. (high : no burst chop, low : burst chopped). see command truth table for details reset input active low asynchronous reset: reset is active when reset is low, and inactive when reset is high. reset must be high during normal operation. reset is a cmos rail to rail signal with dc high and low at 80% and 20% of vdd, i.e. 1.20v for dc high and 0.30v for dc low. dq input/output data input/ output: bi-directional data bus. dqs, (dqs ) input/output data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. tdqs, (tdqs )output termination data strobe: tdqs/tdqs is applicable for x8 drams only. w hen enabled via mode register a11=1 in mr1, dram will enable the same terminat ion resistance function on tdqs/tdqs that is applied to dqs/dqs . when disabled via mode register a11=0 in mr1, dm /tdqs will provide the data mask function and tdqs is not used. nc no connect: no internal electrical connection is present. v ddq supply dq power supply: 1.5v +/- 0.075v v ssq supply dq ground v dd supply power supply: 1.5v +/- 0.075v v ss supply ground v refdq supply reference voltage for dq v refca supply reference voltage for ca zq supply reference pin for zq calibration note : input only pins (ba0-ba2, a0-a12, ras , cas , we , cs , cke, odt and reset ) do not supply termination. 4.0 input/output f unctional description
page 12 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c 512mb * reference information : the following tables ar e address mapping information for other densitites configuration 128mb x4 64mb x 8 32mb x16 # of bank 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 - a 12 a 0 - a 12 a 0 - a 11 column address a 0 - a 9, a 11 a 0 - a 9 a 0 - a 9 bc switch on the fly a 12 /bc a 12 /bc a 12 /bc page size *1 1 kb 1 kb 2 kb 1gb configuration 256mb x4 128mb x 8 64mb x16 # of bank 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 - a 13 a 0 - a 13 a 0 - a 12 column address a 0 - a 9, a 11 a 0 - a 9 a 0 - a 9 bc switch on the fly a 12 /bc a 12 /bc a 12 /bc page size *1 1 kb 1 kb 2 kb 2gb configuration 512mb x4 256mb x 8 128mb x16 # of bank 8 8 8 bank address ba 0 - ba 2 ba 0 - ba 2 ba 0 - ba 2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 - a 14 a 0 - a 14 a 0 - a 13 column address a 0 - a 9, a 11 a 0 - a 9 a 0 - a 9 bc switch on the fly a 12 /bc a 12 /bc a 12 /bc page size 1 kb 1 kb 2 kb 4gb configuration 1gb x4 512mb x 8 256mb x16 # of bank 8 8 8 bank address ba 0 - ba 2 ba 0 - ba 2 ba 0 - ba 2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 - a 15 a 0 - a 15 a 0 - a 14 column address a 0 - a 9, a 11 a 0 - a 9 a 0 - a 9 bc switch on the fly a 12 /bc a 12 /bc a 12 /bc page size 1 kb 1 kb 2 kb 5.0 ddr3 sd ram addressing
page 13 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c note 1 : page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an active comma nd is registered. page size is per bank, calculated as follows: page size = 2 colbits * org 3 8 where, colbits = the number of column address bits, org = the number of i/o (dq) bits 8gb configuration 2gb x4 1gb x 8 512mb x16 # of bank 8 8 8 bank address ba 0 - ba 2 ba 0 - ba 2 ba 0 - ba 2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 - a 15 a 0 - a 15 a 0 - a 15 column address a 0 - a 9, a 11, a 13 a 0 - a 9, a 11 a 0 - a 9 bc switch on the fly a 12 /bc a 12 /bc a 12 /bc page size 2 kb 2 kb 2 kb
page 14 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c 6.1 absolute maximum dc ratings [ table 4 ] absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum ratings? may cause perm anent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicat ed in the operational sections of this s pecification is not implied. exposure to absolute maximum rating conditi ons for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all time s;and vref must be not greater than 0.6xvddq, when vdd and vddq a re less than 500mv; vref may be equal to or less than 300mv. symbol parameter rating units notes vdd voltage on vdd pin relative to vss -0.4 v ~ 1.975 v v 1,3 vddq voltage on vddq pin relative to vss -0.4 v ~ 1.975 v v 1,3 v in, v out voltage on any pin relative to vss -0.4 v ~ 1.975 v v 1 t stg storage temperature -55 to +100 c 7.0 ac & dc operating conditions 7.1 recommended dc operating conditions (sstl_1.5) [ table 6 ] recommended dc operating conditions note : 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.5 1.575 v 1,2 vddq supply voltage for output 1.425 1.5 1.575 v 1,2 [ table 5 ] temperature range note : 1. operating temperature t oper is the case surface temperature on the center/top side of the dram. for measurement condi tions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specifications will be supported. during operation, t he dram case tem- perature must be maintained between 0-85 c under all operating conditions 3. some applications require operation of the extended temperature range between 85 c and 95 c case temperature. full specifications are guaran- teed in this range, but the fo llowing additional conditions apply: a) refresh commands must be doubled in frequency, therefore reduc ing the refresh interval trefi to 3.9us. it is also possibl e to specify a component with 1x refresh (trefi to 7.8us) in the extended temperature r ange. please refer to supplier data sheet and/or the dimm spd for option availability. b) if self-refresh operation is required in the extended temper ature range, then it is mandatory to either use the manual sel f-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b). please refer to the supplier data sheet and/or the dimm spd for auto self-refresh option availability, extended temperatur e range support and trefi requirements in the extended temperature range. symbol parameter rating unit notes t oper normal operating temperature range 0 to 85 c 1,2 extended temperature range (optional) 85 to 95 c 1,3 6.2 dram component operating temperature range 6.0 absolute maximum ratings
page 15 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 7 ] single ended ac and dc input levels note : 1. for dq and dm, v ref = v refdq . for input only pins except reset, or v ref = v refca 2. see 9.6 "overshoot and unders hoot specifications" on page 23. 3. the ac peak noise on v ref may not allow v ref to deviate from v ref(dc) by more than 1% vdd (for reference : approx. 15mv) 4. for reference : approx. vdd/2 15mv symbol parameter ddr3-800/1066/1333 unit notes min. max. v ih (dc) dc input logic high vref + 100 vdd mv 1 v il (dc) dc input logic low vss vref - 100 mv 1 v ih (ac) ac input logic high vref + 175 - mv 1,2 v il (ac) ac input logic low - vref - 175 mv 1,2 v ref dq (dc) i/o reference voltage(dq) 0.49*vddq 0.51*vddq v 3,4 v ref ca (dc) i/o reference voltage(cmd/add) 0.49*vddq 0.51*vddq v 3,4 8.0 ac & dc input measurement levels the dc-tolerance limits and ac-noise limits for the reference voltages v refca and v refdq are illustrate in figure 1. it shows a valid reference voltage vref(t) as a function of time. (vref stands for vrefca and vrefdq likewise). vref(dc) is the linear average of vref(t) over a very long perio d of time (e.g. 1 sec). this average has to meet the min/max requiremts in above table. furthermore vref(t) may temporarily deviate from vref(dc) by no more than 1% vdd. voltage vdd vss v ref ac-noise v ref (dc) v ref (dc)max vdd/2 v ref (dc)min time v ref (dc) 8.1 ac and dc logic input levels for single-ended signals figure 1. illustration of vref(dc) tolerance and vref ac-noise limits the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac) and vil(dc) are dependent on vref. "vref" shall be understood as vref(dc), as defined in figure 1. this clarifies, that dc-varia tions of vref affect the absolute voltage a signal has to reach to achieve a valid high or low le vel and therefore the time to which setup and hold is measured. system timing and voltage budgets need to account for vref(dc) deviations from the optimum po sition within the data-eye of the input signals. this also clarifies that the dram setup/hold specificati on and derating values need to include time and voltage associated wit h vref ac-noise. timing and voltage effects due to ac-noise on vref up to the specified li mit (+/-1% of vdd) are included in dram timings and their ass ociated deratings.
page 16 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c figure 2 : definition of differntial ac-swing and "time above ac level tdvac 0.0 tdvac vihdiff(ac) min vihdiff min vihdiff(dc) min vihdiff(ac) max vihdiff max vihdiff(dc) max differential voltage half cycle time time tdvac ck - ck dqs - dqs [ table 8 ] differential swing requirement for clock (ck - ck ) and strobe (dqs - dqs ) notes: 1. used to define a differential signal slew-rate. 2. for ck - ck use vih/vil(ac) of add/cmd and vrefca; for dqs - dqs , dqsl - dqsl , dqsu - dqsu use vih/vil(ac) of dqs and vrefdq; if a reduced ac-high or ac-low level is used for a si gnal group, then the reduced level applies also here. 3. these values are not defined, however they single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih(dc) max, vil(dc)min) fo r single-ended signals as we ll as the limitations for overshoot and undershoot. [ table 9 ] allowed time before ringback (tdvac) for clk - clk and dqs - dqs . symbol parameter ddr3-800 & 1066 & 1033 & 1600 unit note min max vihdiff differential input high +0.2 note 3 v 1 vildiff differential input low note 3 -0.2 v 1 vihdiff(ac) differential input high ac 2 x (vih(ac)-vref) note 3 v 2 vihdiff(ac) differential input lo w ac note 3 2 x (vref - vil(ac)) v 2 slew rate [v/ns] tdvac [ps] @ |vih/ldiff(ac)| = 350mv tdvac [ps] @ |vih/ldiff(ac)| = 300mv min max min max > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 - 8.2 differential swing requirement for differntial signals
page 17 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c figure 3: single-ended requirement for differential signals. note that while add/cmd and dq signal requirements are with re spect to vref, the single-ended components of differential signal s have a requirement with respect to vdd/2; this is nominally the same. the transition of single-ended signals through the ac-levels i s used to measure setup time. for single-ended components of differential signals the requirement to reach vselmax, vsehmin has no bearin g on timing, but adds a restriction on the comm on mode charateristics of these signals. vdd or vddq vseh min vdd/2 or vddq/2 vsel max vseh vss or vssq vsel ck or dqs time 8.2.1 single-ended requirements for differential signals each individual component of a differential signal (ck, dqs, dqsl, dqsu, ck , dqs , dqsl , or dqsu ) has also to comply with certain requirements for single-ended signals. ck and ck have to approximately reach vsehmin / vselmax (approximately equal to the ac-levels ( vih(ac) / vil(ac) ) for add/cmd signals) in every half-cycle. dqs, dqsl, dqsu, dqs , dqsl have to reach vsehmin / vselmax (approximately t he ac-levels ( vih(ac) / vil(ac) ) for dq signals) in every half-cycle prec eeding and foll owing a valid transition. note that the applicable ac-levels for add/cm d and dq?s might be different per speed-bi n etc. e.g. if vih1 50(ac)/vil150(ac) is used for add/cmd signals, then these ac-levels apply al so for the single-ended signals ck and ck
page 18 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 10 ] differential dc and ac input levels note : 1. refer to "overshoot and undershoot specifications" on page 23. symbol parameter ddr3-800/1066/1333 unit notes min max vihdiff differential i nput logic high + 200 - mv 1 vildiff differential input logic low - - 200 [ table 11 ] cross point voltage for differential input signals (ck, dqs) symbol parameter ddr3-800/1066/1333/1600 unit notes min max vix differential input cross point voltage relative to vdd/2 -150 150 mv to guarantee tight setup and hold times as well as output skew parameters with respect to cl ock and strobe, each cross point vo ltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in below table. the differentia l input cross point voltage vi x is measured from the actual cross point of true and complement signal to the midlevel between of vdd and vss. vdd ck , dqs vdd/2 ck, dqs vss v ix v ix v ix 8.4 differential input cross point voltage figure 4. vix definition 8.3 ac and dc logic input level s for differential signals
page 19 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c 8.5.1 input slew ra te for input setup time (tis) and data setup time (tds) setup (tis and tds) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of vref and the first crossing of vih(ac)min. setup (tis and tds) nominal slew rate for a falling signal is defined as the slew ra te between the last crossing of vref and the first crossing of vil(ac)max. 8.5.2 input slew rate for input hold time (tih) and data hold time (tdh) hold nominal slew rate for a rising signal is defined as the slew rate between the la st crossing of vil(dc)max and the first cr ossing of vref. hold (tih & tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first c rossing of vref [ table 12 ] single ended input slew rate definition notes: this nominal slew rate applies for linear signal waveforms. description measured defined by applicable for from to input slew rate for rising edge vref vih(ac)min vih(ac)min-vref delta trs setup (tis,tds) input slew rate for falling edge vref vil(ac)max vref-vil(ac)max delta tfs input slew rate for rising edge vil(dc)max vref vref-vil(dc)max delta tfh hold (tih,tdh) input slew rate for falling edge vih(dc)min vref vih(dc)min-vref delta trh v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ssq < figure : input slew rate for setup> v swing(max) delta trs delta tfs v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ssq v swing(max) delta trh delta tfh < figure : input slew rate for hold> [ table 13 ] differential input slew rate definition note : the differential signal (i.e. ck - ck and dqs - dqs ) must be linear between these thresholds description measured defined by from to differential input slew rate for rising edge (ck- ck and dqs-dqs ) vildiffmax vihdiffmin vihdiffmin - vildiffmax delta trdiff differential input slew rate for falling edge (ck- ck and dqs-dqs ) vihdiffmin vildiffmax vihdiffmin - vildiffmax delta tfdiff vddq vihdiffmin v ref vildiffmax vssq v swing(max) delta trdiff delta tfdiff 8.5 slew rate definition fo r single ended input signals 8.6 slew rate definition for differential input signals figure 5. input nominal slew rate definition for singel ended signals figure 6. differential input slew rate definition for dqs, dqs and ck, ck
page 20 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 14 ] single ended ac and dc output levels note : 1. the swing of +/-0.1xvddq is based on approximately 50% of the static single ended output high or low swing with a driver imp edance of 34ohms and an effective test load of 25ohms to vtt=vddq/2. symbol parameter ddr3-800/1066/1333/1600 units notes v oh(dc) dc output high measurement level (f or iv curve linearity) 0.8 x vddq v v om(dc) dc output mid measurement level (for iv curve linearity) 0.5 x vddq v v ol(dc) dc output low measurement level (for iv curve linearity) 0.2 x vddq v v oh(ac) ac output high measurement level (for output sr) vtt + 0.1 x vddq v 1 v ol(ac) ac output low measurement level (for output sr) vtt - 0.1 x vddq v 1 [ table 15 ] differential ac and dc output levels note : 1. the swing of +/-0.2xvddq is based on approximately 50% of the static singel ended output high or low swing with a driver imp edance of 34ohms and an effective test load of 25ohms to vtt=vddq/2 at each of the differential outputs symbol parameter ddr3-800/1066/1333/1600 units notes v ohdiff(ac) ac differential output high measurement level (for output sr) +0.2 x vddq v 1 v oldiff(dc) ac differential output low measurement level (for output sr) -0.2 x vddq v 1 9.2 differential ac and dc output levels 9.0 ac and dc output measurement levels 9.1 single ended ac and dc output levels
page 21 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c v ddq v oh(ac) v ref v ol(ac) v ssq delta trs delta tfs 9.4 differential output slew rate with the reference load for timing measurements, output sl ew rate for falling and rising edges is defined and measured between voldiff(ac) and vohdiff(ac) for differential signals as shown intable 18 and figure 8. [ table 18 ] differential output slew rate definition [ table 19 ] differential output slew rate note : output slew rate is verified by design and ch aracterization, and may not be subject to production test. for ron=rzq/7 setting description measured defined by from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) vohdiff(ac)-voldiff(ac) delta trdiff differential output slew rate for falling edge vohdiff(ac) voldiff(ac) vohdiff(ac)-voldiff(ac) delta tfdiff parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max single ended output slew rate srqse 5 10 5 10 5 10 tbd 10 v/ns v ddq v ohdiff(ac) v ref v oldiff(ac) v ssq delta trdiff delta tfdiff figure 7. single ended output slew rate definition figure 8. differential output slew rate definition 9.3.single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac) for single ended signals as shown in table 16 and figure 7. [ table 16 ] single ended output slew rate definition [ table 17 ] single ended output slew rate note : output slew rate is verified by design and char acterization, and may not be subject to production test. for ron=rzq/7 setting description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) delta trse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) delta tfse parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max single ended output slew rate srqse 2.5 5 2.5 5 2.5 5 tbd 5 v/ns
page 22 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c vddq dut dq dqs dqs v tt = v ddq /2 25 ? ck/ck 9.5 reference load for ac timing and output slew rate figure 9 represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of any particular system environment of a depiction of the actual load presented by a production tester. sys- tem designers should use ibis or other simulation tools to corre late the timing reference load to a system environment. manufac turers correlate to their production test conditions, generally on e or more coaxial transmission lines terminated at the tester electronics. figure 9. reference load for ac timing and output slew rate reference point
page 23 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c ac overshoot/undershoot specification for address and control pins (a0-a12, ba0-ba2, cs , ras , cas , we , cke, odt) [ table 20 ] ac overshoot/undershoot specification for address and control pins parameter specification ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 maximum peak amplitude allowed for overshoot area (see figure 8) 0.4v 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure 8) 0.4v 0.4v 0.4v 0.4v maximum overshoot area above vdd (see figure 8) 0.67v-ns 0.5v-ns 0.4v-ns 0.33v-ns maximum undershoot area below vss (see figure 8) 0.67v-ns 0.5v-ns 0.4v-ns 0.33v-ns overshoot area maximum amplitude v dd undershoot area maximum amplitude v ss volts (v) time (ns) ac overshoot/undershoot specification for clock, data, strobe, and mask pins (dq, dqs, dqs , dm, ck, ck) [ table 21 ] ac overshoot/undershoot specification for clock, data, strobe and mask parameter specification ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 maximum peak amplitude allowed for overs hoot area (see figure 9) 0.4v 0.4v 0.4v 0.4v maximum peak amplitude allowed for unders hoot area (see figure 9) 0.4v 0.4v 0.4v 0.4v maximum overshoot area above vddq (see fi gure 9) 0.25v-ns 0.19v-ns 0.15v-ns 0.13v-ns maximum undershoot area below vssq (see figure 9) 0.25v-ns 0.19v-ns 0.15v-ns 0.13v-ns overshoot area maximum amplitude v ddq undershoot area maximum amplitude v ssq volts (v) time (ns) 9.6.2 clock, data, strobe and mask overshoot and undershoot specifications 9.6 overshoot/undershoot specification 9.6.1 address and control overshoot and undershoot specifications figure 10. address and control overshoot and undershoot definition figure 11. clock, data, strobe and mask overshoot and undershoot definition
page 24 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c a functional representation of the output buffer is shown below. output driver impedance ron is defined by the value of externa l reference resistor rzq as follows: ron 34 = rzq/7 (nominal 34ohms +/- 10% with nominal rzq=240ohm) the individual pull-up and pull-down resistor s (ronpu and ronpd) are defined as follows output driver : definition of voltages and currents ronpu = vddq-vout l iout l under the condition that ronpd is turned off ronpd = vout l iout l under the condition that ronpu is turned off vddq dq vssq ron pu ipd ron pd to other circuity output driver ipu iout vout 9.7 34 ohm output driver dc electrical characteristics figure 12. output driver : definition of voltages and currents [ table 22 ] output driver dc electrical characteristics, assuming rzq=240 ohms ; entire operating temperature range; after proper zq calibration note : 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibra- tion, see following section on voltage and temperature sensitivity 2. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss 3. pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 x vddq. other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x vddq and 0.8 x vddq 4. measurement definition for mismatch between pull-up and pull-down, mmpupd: measure ronpu and ronpd. both at 0.5 x vddq: ronpu - ronpd mmpupd = x 100 ronnom ronnom resistor vout min nom max units notes 34ohms ron34pd voldc = 0.2 x vddq 0.6 1.0 1.1 rzq/7 1,2,3 vomdc = 0.5 x vddq 0.9 1.0 1.1 rzq/7 1,2,3 vohdc = 0.8 x vddq 0.9 1.0 1.4 rzq/7 1,2,3 ron34pu voldc = 0.2 x vddq 0.9 1.0 1.4 rzq/7 1,2,3 vomdc = 0.5 x vddq 0.9 1.0 1.1 rzq/7 1,2,3 vohdc = 0.8 x vddq 0.6 1.0 1.1 rzq/7 1,2,3 mismatch between pull-up and pull-down, mmpupd vomdc = 0.5 x vddq -10 10 % 1,2,4
page 25 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c if temperature and/or voltage change after calibration, the tolerance limits widen according to table below ? t = t - t(@calibration); ? v = vddq - vddq (@calibration); vdd = vddq *dr on dt and dr on dv are not subject to production test but are verified by design and characterization [ table 23 ] output dri ver sensitivity definition [ table 24 ] output driver voltage and temperature sensitivity min max units ronpu@v ohdc 0.6 - dr on dth * | ? t| - dr on dvh * | ? v| 1.1 + dr on dth * | ? t| + dr on dvh * | ? v| rzq/7 ron@v omdc 0.9 - dr on dtm * | ? t| - dr on dvm * | ? v| 1.1 + dr on dtm * | ? t| + dr on dvm * | ? v| rzq/7 ronpd@ voldc 0.6 - dr on dtl * | ? t| - dr on dvl * | ? v| 1.1 + dr on dtl * | ? t| + dr on dvl * | ? v| rzq/7 min max units dr on dtm 01.5 %/ c dr on dvm 0 0.15 %/mv dr on dtl 01.5 %/ c dr on dvl 0tbd%/mv dr on dth 01.5 %/ c dr on dvh 0tbd%/mv 9.7.1 output drive temperature and voltage sensitivity on-die termination effective resistance rtt is defined by bits a9, a6 and a2 of mr1 register. odt is applied to the dq,dq, dqs/dqs and tdqs,tdqs (x8 devices only) pins. a functional representation of the on-die termination is sh own below. the individual pull-up and pull-down resistors ( rttpu and rttpd ) are defined as follows : on-die termination : definiti on of voltages and currents rttpu = vddq-vout l iout l under the condition that rttpd is turned off rttpd = vout l iout l under the condition that rttpu is turned off vddq dq vssq rtt pu ipd rtt pd to other circuitry like rcv, ... output driver ipu iout vout iout=ipd-ipu 9.8 on-die termination (odt) levels and i-v characteristics figure 13. on-die termination : definitionof voltages and currents
page 26 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c table # provides and overview of the odt dc el ectrical characteristics. they values for rtt 60pd120, rtt 60pu120, rtt 120pd240, rtt 120pu240, rtt 40pd80, rtt 40pu80, rtt 30pd60, rtt 30pu60, rtt 20pd40, rtt 20pu40 are not specification requirements, but can be used as design guide lines:. [ table 25 ] odt dc electrical characteristics, assuming rzq=240 oh m +/- 1% entire operating temperature range; after proper zq calibration mr1 (a9,a6,a2) rtt resistor vout min nom max unit notes (0,1,0) 120 ohm rtt 120pd240 0.2xvddq 0.6 1.0 1.1 r zq 1,2,3,4 0.5xvddq 0.9 1.0 1.1 r zq 1,2,3,4 0.8xvddq 0.9 1.0 1.4 r zq 1,2,3,4 rtt 120pu240 0.2xvddq 0.9 1.0 1.4 r zq 1,2,3,4 0.5xvddq 0.9 1.0 1.1 r zq 1,2,3,4 0.8xvddq 0.6 1.0 1.1 r zq 1,2,3,4 rtt 120 v il( ac ) to v ih( ac ) 0.9 1.0 1.6 r zq /2 1,2,5 (0,0,1) 60 ohm rtt 60pd240 0.2xvddq 0.6 1.0 1.1 r zq /2 1,2,3,4 0.5xvddq 0.9 1.0 1.1 r zq /2 1,2,3,4 0.8xvddq 0.9 1.0 1.4 r zq /2 1,2,3,4 rtt 60pu240 0.2xvddq 0.9 1.0 1.4 r zq /2 1,2,3,4 0.5xvddq 0.9 1.0 1.1 r zq /2 1,2,3,4 0.8xvddq 0.6 1.0 1.1 r zq /2 1,2,3,4 rtt 60 v il( ac ) to v ih( ac ) 0.9 1.0 1.6 r zq /4 1,2,5 (0,1,1) 40 ohm rtt 40pd240 0.2xvddq 0.6 1.0 1.1 r zq /3 1,2,3,4 0.5xvddq 0.9 1.0 1.1 r zq /3 1,2,3,4 0.8xvddq 0.9 1.0 1.4 r zq /3 1,2,3,4 rtt 40pu240 0.2xvddq 0.9 1.0 1.4 r zq /3 1,2,3,4 0.5xvddq 0.9 1.0 1.1 r zq /3 1,2,3,4 0.8xvddq 0.6 1.0 1.1 r zq /3 1,2,3,4 rtt 40 v il( ac ) to v ih( ac ) 0.9 1.0 1.6 r zq /6 1,2,5 (1,0,1) 30 ohm rtt 60pd240 0.2xvddq 0.6 1.0 1.1 r zq /4 1,2,3,4 0.5xvddq 0.9 1.0 1.1 r zq /4 1,2,3,4 0.8xvddq 0.9 1.0 1.4 r zq /4 1,2,3,4 rtt 60pu240 0.2xvddq 0.9 1.0 1.4 r zq /4 1,2,3,4 0.5xvddq 0.9 1.0 1.1 r zq /4 1,2,3,4 0.8xvddq 0.6 1.0 1.1 r zq /4 1,2,3,4 rtt 60 v il( ac ) to v ih( ac ) 0.9 1.0 1.6 r zq /8 1,2,5 (1,0,0) 20 ohm rtt 60pd240 0.2xvddq 0.6 1.0 1.1 r zq /6 1,2,3,4 0.5xvddq 0.9 1.0 1.1 r zq /6 1,2,3,4 0.8xvddq 0.9 1.0 1.4 r zq /6 1,2,3,4 rtt 60pu240 0.2xvddq 0.9 1.0 1.4 r zq /6 1,2,3,4 0.5xvddq 0.9 1.0 1.1 r zq /6 1,2,3,4 0.8xvddq 0.6 1.0 1.1 r zq /6 1,2,3,4 rtt 60 v il( ac ) to v ih( ac ) 0.9 1.0 1.6 r zq /12 1,2,5 deviation of vm w.r.t vddq/2, ? vm -5 5 % 1,2,5,6 9.8.1 odt dc electrica l characteristics
page 27 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c note : 1. the tolerance limits are specified af ter calibration with stable voltage and temper ature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following sect ion on voltage and temperature sensitivity 2. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss 3. pull-down and pull-up odt resistors are recommended to be calibr ated at 0.5xvddq. other calibration schemes may be used to a chieve the linearity spec shown above, e.g. calibration at 0.2xvddq and 0.8xvddq. 4. not a specification requirement, but a design guide line 5. measurement definition for rtt: apply vih(ac) to pin under test and measure current i(vi h(ac)), then apply vil(ac) to pin under test and measure current i( vil(ac)) perspectively 6. measurement definition for vm and ? vm : measure voltage (vm) at test pin (midpoint) with no load rtt = vih(ac) - vil(ac) i(vih(ac)) - i(vil(ac)) ? vm = 2 x vm vddq x 100 - 1 if temperature and/or voltage change after calibration, the tolerance limits widen according to table below ? t = t - t(@calibration); ? v = vddq - vddq (@calibration); vdd = vddq [ table 26 ] odt sensitivity definition [ table 27 ] odt voltage and temperature sensitivity these parameters may not be subject to production te st. they are verified by design and characterization. min max units rtt 0.9 - dr tt dt * | ? t| - dr tt dv * | ? v| 1.6 + dr tt dt * | ? t| + dr tt dv * | ? v| rzq/2,4,6,8,12 min max units dr tt dt 01.5 %/ c dr tt dv 0 0.15 %/mv 9.8.2 odt temperature and voltage sensitivity
page 28 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c vddq ck,ck dut dq, dm dqs , dqs tdqs , tdqs rtt =25 ohm vtt= vssq timing reference points bd_refload_odt 9.9.2 odt timing definition definitions for t aon , t aonpd , t aof , t aofpd and t adc are provided in table28 and subsequent figures. measurement reference settings are provided in table29. [ table 28 ] odt timing definitions [ table 29 ] reference settings for odt timing measurements symbol begin point definition end point definition figute t aon rising edge of ck - ck defined by the end point of odtlon extrapolated point at vssq figure 2 t aonpd rising edge of ck - ck with odt being first registered high extrapolated point at vssq figure 3 t aof rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom figure 4 t aofpd rising edge of ck - ck with odt being first registered low end point: extrapolated point at vrtt_nom figure 5 t adc rising edge of ck - ck defined by the end point of odtlcnw, odtlcwn4 of odtlcwn8 end point: extrapolated point at vrtt_wr and vrtt_nom respectively figure 6 measured parameter rtt_nom setting rtt_wr setting v sw1 [v] v sw2 [v] note t aon r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aonpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aof r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aofpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t adc r zq /12 r zq /2 0.20 0.30 vssq figure 14. odt timing reference load 9.9 odt timing definitions 9.9.1 test load for odt timings different than for timing measurements, the refer ence load for odt timings is defined in figure 14.
page 29 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c ck ck begin point : rising edge of ck - ck defined by the end point of odtlon t aon vtt dq, dm dqs , dqs tdqs , tdqs vssq t sw1 t sw2 v sw1 v sw2 end point extrapolated point at vssq vssq ck ck begin point : rising edge of ck - ck with odt being first registered high t aonpd vtt dq, dm dqs , dqs tdqs , tdqs vssq t sw1 t sw2 v sw1 v sw2 end point extrapolated point at vssq vssq ck ck begin point : rising edge of ck - ck defined by the end point of odtloff t aof vtt dq, dm dqs , dqs tdqs , tdqs vrtt_nom t sw1 t sw2 v sw1 v sw2 end point extrapolated point at vrtt_nom vssq td_taon_def figure 15. definition of taon figure 16. definition of taonpd figure 17. definition of taof
page 30 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c ck ck begin point : rising edge of ck - ck with odt being first registered low t aofpd vtt dq, dm dqs , dqs tdqs , tdqs vrtt_nom t sw1 t sw2 v sw1 v sw2 end point extrapolated point at vrtt_nom vssq ck ck begin point : rising edge of ck - ck defined by the end point of odtlcnw t adc vtt dq, dm dqs , dqs tdqs , tdqs vrtt_nom t sw11 t sw21 v sw1 end point extrapolated point at vrtt_nom vrtt_wr end point extrapolated point at vrtt_wr t adc v sw2 begin point : rising edge of ck - ck defined by the end point of odtlcwn4 or odtlcwn8 end point extrapolated point at vrtt_nom t sw12 t sw22 vrtt_nom vssq figure 18. definition of taofpd figure 19. definition of tadc
page 31 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c 10.1 idd measurement conditions within the tables provided further down, an overview about the idd measurement conditi ons is provided as follows: [ table 30 ] overview of tables providing idd measurement conditions and dram behavior within the tables about idd measurement conditions, the following definitions are used: ? low is defined as v in <= v ilac (max.); high is defined as v in >= v ihac (min.); ? stable is defined as inputs are stable at a high or low level ? floating is defined as inputs are v ref = v ddq / 2 ? switching is defined as descri bed in the following 2 tables. [ table 31 ] definition of switching for address and command input signals [ table 32 ] definition of switching for data (dq) table number measurement conditions table 34 idd0 and idd1 table 35 idd2n, idd2q, idd2p(0), idd2p(1) table 36 idd3n and idd3p table 37 idd4r, idd4w, idd7 table 38 idd7 for different speed grades and different trrd, tfaw conditions table 39 idd5b table 40 idd6, idd6et switching for address (row, column) and command signals (cs , ras , cas , we ) is defined as: address (row, column): if not otherwise mentioned the inputs are stable at high or low during 4 clocks and change then to the opposite value (e.g. ax ax ax ax ax ax ax ax ax ax ax ax ..... please see each iddx definition for details bank address: if not otherwise mentioned the bank add resses should be switched like the row/ column addresses - please see each iddx definition for details command (cs , ras , cas , we ): define d = {cs , ras , cas , we } := {high, low, low, low} define d = {cs , ras , cas , we } := {high, high,high,high} define command background pattern = d d d d d d d d d d d d ... if other commands are necessary (e.g. act for idd0 or read for idd4r) the background pattern command is substituted by the respective cs , ras , cas , we levels of the necessary command. see each iddx definition for details and figures 1,2,3 as examples. switching for data (dq) is defined as data (dq) data dq is changing between high and low every other data transfer (once per clock) for dq signals, which means that data dq is stable during one clock; se e each iddx definition for exceptions from this rule and for further details. see figures 1,2,3 as examples. data masking (dm) no switching; dm must be driven low all the time 10.0 idd specification parameters and test conditions
page 32 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c timing parameters are listed in the following table: [ table 33 ] for idd testing the following parameters are utilized. the following conditions apply: 1. idd specifications are tested afte r the device is properly initialized. 2. input slew rate is specified by ac parametric test conditions. 3. idd parameters are specified with odt and output buffer disabled (mr1 bit a12). parameter bin ddr3-800 ddr3-1066 ddr3-1333 unit 6-6-6 7-7-7 8-8-8 8-8-8 9-9-9 t ckmin (idd) 2.5 1.875 1.5 ns cl(idd) 6 7889 t rcdmin (idd) 15 13.13 15 12 13.5 ns t rcmin (idd) 52.5 50.63 52.50 48 49.5 ns t rasmin (idd) 37.5 37.5 37.5 36 36 ns t rpmin (idd) 15 13.13 15 12 13.5 ns t faw (idd) x4/x8 40 37.5 37.5 30 30 ns x16 50 50504545ns t rrd (idd) x4/x8 10 7.5 7.5 6.0 6.0 ns x16 10 10 10 7.5 7.5 ns t rfc (idd) - 1gb 110 110 110 110 110 110
page 33 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 34 ] idd measurement conditions for idd0 and idd1 current idd0 idd1 name operating current 0 -> one bank activate -> precharge operating current 1 -> one bank activate -> read -> precharge measurement condition timing diagram example figure 1 cke high high external clock on on t ck t ck min(idd) t ck min(idd) t rc t rc min(idd) t rc min(idd) t ras t ras min(idd) t ras min(idd) t rcd n.a. t rcd min(idd) t rrd n.a. n.a. cl n.a. cl(idd) al n.a. 0 cs high between. activate and precharge commands high between activate, read and precharge command inputs (cs , ras , cas , we ) switching as described in table 2; only exceptions are activate and precharge com- mands; example of idd0 pattern: a0 d d d d d d d d d d d p0 (ddr3-800: tras = 37.5ns between (a)ctivate and (p)recharge to bank 0 ; definition of d and d: see table 2) definition of d and d : see table ##. switching as described in table 2; only exceptions are activate, read and precharge commands; example of idd1 pattern: a0 d d d d r0 d d d dd d d dd d p0 (ddr3-800 -555: trcd = 12.5ns between (a)ctivate and (r)ead to bank 0 ; definition of d and d: see table 2) definition of d and d : see table ##. row, column addresses row addresses switching as described in table 2; address input a10 must be low all the time! row addresses switching as described in table 2; address input a10 must be low all the time! bank addresses bank address is fixed ( bank 0) bank address is fixed (bank 0) data i/o switching as described in table 3 read data: output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to "1". when there is no read data burst from dram the dq i/o should be floating. output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 rtt_nom, rtt_wr disabled disabled burst length n.a. 8 fixed / mr0 bits [a1, a0] = {0,0} active banks one act-pre loop one act-rd-pre loop idle banks all other all other precharge power down mode / mode register bit 12 n.a. n.a.
page 34 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 ck t17 t18 act 000 idd1 measurement loop ba[2:0] addr_a[9:0] addr_b[10] addr_c[13:11] cs ras cas we cmd dq dm 3ff 000 000 3ff 000 111 000 000 111 000 d d rd d d d d d d d d d pre d d d d d 0 0 1 1 0 0 1 1 figure 20. idd1 example (ddr3-800-666, 1gb x8): data dq is shown but the output buffer should be switched off (per mr1 bit a12 ="1") to achieve iout = 0ma. address inputs are split into 3 parts.
page 35 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 35 ] idd measurement conditions for idd2n, idd2p(1), idd2p(0) and idd2q note : 1. in ddr3 the mrs bit 12 defines dll on/off behavior only for pr echarge power down. there are 2 different precharge power down states possible : one with dll on (fast exit, bit 12 = 1) and one with dll off (slow exit, bit 12 = 0). 2. because it is an exit after precharge power down the valid commands are: activate, refresh, mode-register set, enter - self refresh. current idd2n idd2p(1) a idd2p(0) idd2q name precharge standby current precharge power down current fast exit - mrs a12 bit = 1 precharge power down current slow exit - mrs a12 bit = 0 precharge quiet standby current measurement condition timing diagram example figure 2 cke high low low low external clock on on on on t ck t ckmin (idd) t ckmin (idd) t ckmin (idd) t ckmin (idd) t rc n.a. n.a. n.a. n.a. t ras n.a. n.a. n.a. n.a. t rcd n.a. n.a. n.a. n.a. t rrd n.a. n.a. n.a. n.a. cl n.a. n.a. n.a. n.a. al n.a. n.a. n.a. n.a. cs high stable high stable bank address, row addr. and command inputs switching as described in table 2 stable stable stable data inputs switching floating floating floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 off / 1 rtt_nom, rtt_we disabled disabled disabled disabled burst length n.a. n.a. n.a. n.a. active banks none none none none idle banks all all all all precharge power down mode / mode register bit a n.a. fast exit / 1 (any valid command after txp 1 ) slow exit / 0 slow exit (rd and odt commands must satisfy txpdll-al) n.a. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 ck 0 idd2n /idd3n measurement loop ba[2:0] addr[13:0] cs ras cas we cmd dq[7:0] dm 7 0 0000 3fff 0000 d d d d figure 21. idd2n /idd3n example (ddr3-800-666, 1gb x8) d d d d d d d ff 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff 00
page 36 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table36 ] idd measurement conditions for idd3n and idd3p(fast exit) note : 1. ddr3 will offer only one active power down mode with dll on (-> fast exit). mrs bit 12 will not be used for active power dow n. instead bit a12 will be used to switch between two different precharge power down modes. current idd3n idd3p name active standby current active power-down current a always fast exit measurement condition timing diagram example figure 2 cke high low external clock on on t ck t ckmin (idd) t ckmin (idd) t rc n.a. n.a. t ras n.a. n.a. t rcd n.a. n.a. t rrd n.a. n.a. cl n.a. n.a. al n.a. n.a. cs high stable addr. and cmd inputs switching as described in table 2 stable data inputs switching as described in table 3 floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 rtt_nom, rtt_we disabled disabled burst length n.a. n.a. active banks all all idle banks none none precharge power down mode / mode register bit a n.a. n.a. (active power down mode is always "fast exit" with dll on
page 37 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 37 ] idd measurement conditions for idd4r, idd4w and idd7 current idd4r idd4w idd7 name operating current burst read operating current burst write all bank interleave read current measurement condition timing diagram example figure 3 cke high high high external clock on on on t ck t ckmin (idd) t ckmin (idd) t ckmin (idd) t rc n.a. n.a. t rcmin (idd) t ras n.a. n.a. t rasmin (idd) t rcd n.a. n.a. t rcdmin (idd) t rrd n.a. n.a. t rrdmin (idd) cl cl(idd) cl(idd) cl(idd) al 0 0 t rcdmin -1t ck cs high btw. valid cmds high btw. valid cmds high btw. valid cmds command inputs (cs , ras , cas , we ) switching as described in table 2; exceptions are read commands => idd4r pattern: r0ddd r1dddr3 ddd r3ddd r4 ..... rx = read from bank x; definition of d and d: see table 2 switching as described in table 2; exceptions are write commands => idd4w pattern: w0ddd w1ddd w2ddd w3ddd w4 ... wx = write to bank x; definition of d and d: see table 2 for patterns see table 9 row, column addresses column addresses switching as described in table 2; address input a10 must be low all the time! column addresses switching as described in table 2; address input a10 must be low all the time! stable during deselects bank addresses bank address cycling (0 ->1 -> 2 -> 3 ...) bank address cycling (0 ->1 -> 2 -> 3 ...) bank address cycling (0 ->1 -> 2 -> 3 ...), see pattern in table 9 dq i/o seamless read data burst (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to "1". seamless write data burst (bl8): input data switches every clock, which means that write data is stable during one clock cycle. dm is low all the time. read data (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to "1". output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 rtt_nom, rtt_we dis abled disabled disabled burst length 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} active banks all all all idle banks none none none precharge power down mode / mode register bit n.a. n.a. n.a.
page 38 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 ck 000 start of measurement loop ba[2:0] addr_a[9:0] cs ras cas we cmd[2:0] dq[7:0] dm 001 010 000 3ff 000 rd d d rd figure 22 idd4r example (ddr3-800-666,1gb x8): data dq is shown but the output buffer should be switched off (per mr1 bit a12="1") to achieve iout = 0ma. address inputs are split into 3 parts. d d d rd d d 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 t11 t12 t13 001 3ff addr_b[10] addr_c[13:11] 000 111 000 111 d d rd d [ table 38 ] idd7 pattern for different speed grades and different trrd, tfaw conditions note : 1. a0 = activation of bank 0; ra0 = read with auto-precharge of bank 0; d = deselect speed bin org. tfaw tfaw trrd trrd idd7 pattern a mb/s [ns] [clk] [ns] [clk] 800 all x4/x8 40 16 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 dd a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7d d all x16 50 20 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 dd d d d d a4 ra4 d d a5 ra5 d d a6 ra6 dd a7 ra7 d d d d d d 1066 all x4/x8 37.5 20 7.5 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 dd d d d d a4 ra4 d d a5 ra5 d d a6 ra6 dd a7 ra7 d d d d d d all x16 50 27 10 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d dd d a3 ra3 d d d d d d d a4 ra4 d d d d a5ra5 d d d d a6 ra6 d d d d a7 ra7 d d d dd d d 1333 all x4/x8 30 20 6 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 dd d d d d a4 ra4 d d a5 ra5 d d a6 ra6 dd a7 ra7 d d d d d d all x16 45 30 7.5 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3ra3 d d d d d d d d d d d d d a4 ra4 d d da5 ra5 d d d a6 ra6 d d d a7 ra7 d d d dd d d d d d d d d 1600 all x4/x8 30 24 6 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3ra3 d d d d d d d a4 ra4 d d d a5 ra5 d dd a6 ra6 d d d a7 ra7 d d d d d d d all x16 40 32 7.5 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d dd d a3 ra3 d d d d d d d d d d d d a4 ra4d d d d a5 ra5 d d d d a6 ra6 d d d d a7ra7 d d d d d d d d d d d d
page 39 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 39 ] idd measurement conditions for idd5b current idd5b name burst refresh current measurement condition cke high external clock on t ck t ckmin (idd) t rc n.a. t ras n.a. t rcd n.a. t rrd n.a. t rfc t rfcmin (idd) cl n.a. al n.a. cs high btw. valid cmds addr. and cmd inputs switching data inputs switching output buffer dq,dqs / mr1 bit a12 off / 1 rtt_nom, rtt_we disabled burst length n.a. active banks refresh command every t rfc =t rfc min idle banks none precharge power down mode / mode register bit n.a.
page 40 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 40 ] idd measurement conditions for idd6 and idd6et note : 1 .users should refer to the dram supplier datasheet and/or th e dimm spd to determine if ddr3 sdram devices support the followi ng options referred to in this material current idd6 idd6et name self-refresh current normal temperature range tcase = 0 .. 85c self-refresh current extended temperature range a tcase = 0 .. 95c measurement condition temperature tcase = 85c tcase = 95c auto self refresh(asr) / mr2 bit a6 disabled / "0" disabled / "0" self refresh temperature range (srt) / mr2 bit a7 normal / "0" enabled / "1" cke low low external clock off; ck and ck at low off; ck and ck at low t ck n.a. n.a. t rc n.a. n.a. t ras n.a. n.a. t rcd n.a. n.a. t rrd n.a. n.a. cl n.a. n.a. al n.a. n.a. cs floating floating command inputs (cs , ras , cas , we ) floating floating row, column addresses floating floating bank addresses floating floating data i/o floating floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 rtt_nom, rtt_wr disabled disabled burst length n.a. n.a. active banks all during self-refresh ac tions all during self-refresh actions idle banks all btw. self-refresh actions all btw. self-refresh actions precharge power down mode / mode register bit 12 n.a. n.a. [ table 41 ] idd6 current definition symbol parameter/condition idd6 normal temperature range self-refresh current : cke< 0.2v; external clock off, ck and ck at 0v; other control and address inputs are floating; data bus inputs are floating, pasr disabled. applicable for mr2 setting a6=0 and a7=0. idd6et extended temperature range self-refresh current: cke<0.2v; ex ternal clock off, ck and ck at 0v; other control and address inputs are floating; data bus inputs are floating, pasr disabled. applicable for mr2 settings a6=0 and a7=1.
page 41 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c (idd values are for full operating range of voltage and temperature) [ table 42 ] idd specification symbol conditions units notes idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 8, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are sw itching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are sw itching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 8, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; a ddress bus inputs are switching;data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 8, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t ras- max(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switch- ing; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and address bus inputs are sw itching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating ma idd6et extended temperature range self-refresh current ; ck and ck at 0v; cke 0.2v; other control and address inputs are floating; data bus inputs are floating, pasr disabled, applicable for mr2 setting a6=0 and a7=1 ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 8, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; ma 10.2 idd specifications
page 42 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 43 ] idd specification for 1gb ddr3 c-die symbol 256mx4 (k4b1g0446c) unit notes 800mbps 1066mbps 1333mbps 6-6-6 7-7-7 8-8-8 8-8-8 9-9-9 idd0 tbd tbd tbd tbd tbd ma idd1 tbd tbd tbd tbd tbd ma idd2p-f tbd tbd tbd tbd tbd ma idd2p-s tbd tbd tbd tbd tbd ma idd2n tbd tbd tbd tbd tbd ma idd2q tbd tbd tbd tbd tbd ma idd3p-f tbd tbd tbd tbd tbd ma idd3n tbd tbd tbd tbd tbd ma idd4r tbd tbd tbd tbd tbd ma idd4w tbd tbd tbd tbd tbd ma idd5 tbd tbd tbd tbd tbd ma idd6 tbd tbd tbd tbd tbd ma idd6et tbd tbd tbd tbd tbd ma idd7 tbd tbd tbd tbd tbd ma symbol 128mx8 (k4b1g0846c) unit notes 800mbps 1066mbps 1333mbps 6-6-6 7-7-7 8-8-8 8-8-8 9-9-9 idd0 tbd tbd tbd tbd tbd ma idd1 tbd tbd tbd tbd tbd ma idd2p-f tbd tbd tbd tbd tbd ma idd2p-s tbd tbd tbd tbd tbd ma idd2n tbd tbd tbd tbd tbd ma idd2q tbd tbd tbd tbd tbd ma idd3p-f tbd tbd tbd tbd tbd ma idd3n tbd tbd tbd tbd tbd ma idd4r tbd tbd tbd tbd tbd ma idd4w tbd tbd tbd tbd tbd ma idd5 tbd tbd tbd tbd tbd ma idd6 tbd tbd tbd tbd tbd ma idd6et tbd tbd tbd tbd tbd ma idd7 tbd tbd tbd tbd tbd ma symbol 64mx16 (k4b1g1646c) unit notes 800mbps 1066mbps 1333mbps 6-6-6 7-7-7 8-8-8 8-8-8 9-9-9 idd0 tbd tbd tbd tbd tbd ma idd1 tbd tbd tbd tbd tbd ma idd2p-f tbd tbd tbd tbd tbd ma idd2p-s tbd tbd tbd tbd tbd ma idd2n tbd tbd tbd tbd tbd ma idd2q tbd tbd tbd tbd tbd ma idd3p-f tbd tbd tbd tbd tbd ma idd3n tbd tbd tbd tbd tbd ma idd4r tbd tbd tbd tbd tbd ma idd4w tbd tbd tbd tbd tbd ma idd5 tbd tbd tbd tbd tbd ma idd6 tbd tbd tbd tbd tbd ma idd6et tbd tbd tbd tbd tbd ma idd7 tbd tbd tbd tbd tbd ma 1gb ddr3 sdram e-die idd spec table
page 43 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 44 ] input / output capacitance note : 1. although the dm, tdqs and tdqs# pins have differ ent functions, the loading matches dq and dqs 2. this parameter is not subject to production test. it is verified by design and characterization. the capacitance is measured according to jep147("procedure for measuring inpu t capacitance using a vector network analyzer( vna)") with vdd, vddq, vss, vssq applied and all other pins floating (except the pin under test, cke, reset# and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to monolithic devices on ly; stacked/dual-die devices are not covered here 4. absolute value of cck-cck# 5. absolute value of cio(dqs)-cio(dqs#) 6. ci applies to odt, cs#, cke, a0-a15, ba0-ba2, ras#, cas#, we#. 7. cdi_ctrl applies to odt, cs# and cke 8. cdi_ctrl=ci(ctrl)-0.5*(ci(clk)+ci(clk#)) 9. cdi_add_cmd applies to a0-a15, ba0-ba2, ras#, cas# and we# 10. cdi_add_cmd=ci(add_cmd) - 0.5*(ci(clk)+ci(clk#)) 11. cdio=cio(dq,dm) - 0.5*(cio(dqs)+cio(dqs#)) parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio 1.5 3.0 1.5 3.0 1.5 2.5 tbd tbd pf 1,2,3 input capacitance (ck and ck) cck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pf 2,3,5 input capacitance delta (ck and ck) cdck 0 0.15 0 0.15 0 0.15 0 0.15 pf 2,3,4 input capacitance (all other input-only pins) ci 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 pf 2,3,6 input capacitance delta (dqs and dqs) cddqs 0 0.2 0 0.2 0 0.15 0 0.15 pf 2,3,12 input capacitance delta (all control input-only pins) cdi_ctrl -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 pf 2,3,7,8 input capacitance delta (all add and cmd input-onlypins) cdi_add_cmd -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 pf 2,3,9,10 input/output capacitance delta (dq, dm, dqs, dqs , tdqs, tdqs ) cdio -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pf 2,3,11 input/output capacitance of zq pin czq - 3 - 3 - 3 - 3 pf 2, 3, 13 11.0 input/output capacitance
page 44 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c 12.1 clock specification [ table 45 ] clock specification add note fot tck(avg) tck(avg) is calculated as the average cl ock period across any consec utive 200 cycle window, where eac h clock period is calculat ed from rising edge to rising edge. add note fot tck(abs) tck(abs) is the absolute clock peri od, as measured from one rising edge to the next consecutive rising edge. parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max average clock period tck(avg) 2500 3333 1875 3333 1500 3333 1250 3333 ps clock period tck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps n j=1 tckj n n=200 12.0 electrical characteris tics and ac timing fo r ddr3-800 to ddr3-1600
page 45 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 46 ] clock jitter specification note : the jitter specified is a random jitter meeting a gaussian distribution. input clocks violating the min/max values may r esult in malfunction of the ddr3 sdram device. add note for tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated acro ss any consecutive 200 high pulses: tcl(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses: add note for tjit(duty) tjit(duty) is defined as the cumulative set of tch jitter and tc l jitter. tch jitter is the largest deviation of any single tc h form tch(avg). tcl jitter is the largest deviation of any single tcl from tcl(avg) tjit(duty) = min/max of {tjit(ch), tjit(cl)}, where: tjit(ch) = {tchi-tch(avg) where i=1 to 200}, tjit(cl) = {tcli-tcl(avg) where i=1 to 200}, add note for tjit(per), tjit(per,lck) tjit(per) is defined as the largest deviation of any single tck from tck(avg). tjit(per) = min/max of {tcki-tck(avg) where i=1 to 200} tjit(per) defines the single period jitter when the dll is already locked. tjit(per,lck) uses the same definition for singl e period jitter, during the dll locking period only. tjit(per) and tjit(per,lck) are not guar anteed through final production testing add note for tjit(cc), tjit(cc,lck) tjit(cc) is defined as the absolute differ ence in clock period between two consecutive clock cycles: tjit(cc) = max of {tcki+1 -tcki} tjit(cc) defines the cycl e to cycle jitter when the dll is already locked. tjit(cc,lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. tjit(cc) and tjit(cc,lck) are not gua ranteed through final production testing add note for terr(nper) terr is defined as the cumulative error across n multiple consecutive cycles from tck(av g). this definition is tbd. parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max clock period jitter tjit(per) -100 100 -90 90 -80 80 -70 70 ps clock period jitter during dll lock- ing period tjit(per,lck) -90 90 -80 80 -70 70 -60 60 ps cycle to cycle clock period jitter tjit(cc) 200 180 160 140 ps cycle to cycle clock period jitter during dll locking period tjit(cc,lck) 180 160 140 120 ps cumulative error across n cycles terr(nper) tbd tbd tbd tbd tbd tbd tbd tbd ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) duty cycle jitter tjit(duty) -100 100 -75 75 -60 60 -50 50 ps n j=1 tchj n x tck(avg) n=200 n j=1 tclj n x tck(avg) n=200 12.2 clock jitter specification
page 46 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 47 ] refresh parameters by device density parameter symbol 512mb 1gb 2gb 4gb 8gb units all bank refresh to active/refresh cmd time trfc 90 110 160 300 350 ns average periodic refresh interval trefi 0 c t case 85 c 7.8 7.8 7.8 7.8 7.8 s 85 c < t case 95 c 3.9 3.9 3.9 3.9 3.9 s 12.4 standard speed bins ddr3 sdram standard speed bins include tck, t rcd, trp, tras and trc for each corresponding bin. [ table 48 ] ddr3-800 speed bins speed ddr3-800 units note cl-nrcd-nrp 6 - 6 - 6 parameter symbol min max intermal read command to first data t aa 15 20 ns act to internal read or write delay time t rcd 15 - ns pre command period t rp 15 - ns act to act or ref command period t rc 52.5 - ns act to pre command period t ras 37.5 9*trefi ns 8 cl = 5 / cwl = 5 t ck(avg) reserved ns 1,2,3,4 cl = 6 / cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3 supported cl settings 6 n ck supported cwl settings 5 n ck [ table 49 ] ddr3-1066 speed bins speed ddr3-1066 ddr3-1066 units note cl-nrcd-nrp 7 - 7 - 7 8 - 8 - 8 parameter symbol min max min max intermal read command to first data t aa 13.125 20 15 20 ns act to internal read or write delay time t rcd 13.125 - 15 - ns pre command period t rp 13.125 - 15 - ns act to act or ref command period t rc 50.625 - 52.5 - ns act to pre command period t ras 37.5 9*trefi 37.5 9*trefi ns 8 cl = 5 cwl = 5 t ck(avg) reserved reserved ns 1,2,3,4,6 cwl = 6 t ck(avg) reserved reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 ns 1,2,3,6 cwl = 6 t ck(avg) reserved reserved ns 1,2,3,4 cl = 7 cwl = 5 t ck(avg) reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 <2.5 reserved ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 <2.5 1.875 <2.5 ns 1,2,3 supported cl settings 6,7,8 6,8 n ck supported cwl settings 5,6 5,6 n ck 12.3 refresh parameters by device density
page 47 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c notes : absolute specification (to per;vddq=vdd=1.5v +/- 0.075v); 1. the cl setting and cwl setting result in tck(avg).min and tc k(avg).max requirements. when making a selection of tck(avg), bo th need to be ful- filed: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely analog - data and strobe output are synchronized by the dll - all possi ble intermediate frequen- cies may not be guaranteed. an application should use the next sm aller jedec standard tck(avg) value (2.5, 1.875, 1.5, or 1.25 ns) when calculat- ing cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next ?supported cl?. 3. tck(avg).max limits: calculat e tck(avg) = taa.max / clselected and round the resulting tck(avg) down to the next valid speed bin limit (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to clselected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow cert ain devices in the industry to support this setting, however, it is not a mandatory feature. r efer to supplier?s data sheet and spd information if and how this setting is supported. 6. any ddr3-1066 speed bin also supports func tional operation at lower frequencies as s hown in the table which are not subject to production tests but verified by design/characterization. 7. any ddr3-1333 speed bin also supports func tional operation at lower frequencies as s hown in the table which are not subject to production tests but verified by design/characterization. 8. trefi depends on toper [ table 50 ] ddr3-1333 speed bins speed ddr3-1333 ddr3-1333 units note cl-nrcd-nrp 8 - 8 - 8 9 -9 - 9 parameter symbol min max min max intermal read command to first data t aa 12 20 13.5 20 ns act to internal read or write delay time t rcd 12 - 13.5 - ns pre command period t rp 12 - 13.5 - ns act to act or ref command period t rc 48 - 49.5 - ns act to pre command period t ras 36 9*trefi 36 9*trefi ns 8 cl = 5 cwl = 5 t ck(avg) 2.5 3.3 reserved ns 1,2,3,4,7 cwl = 6,7 t ck(avg) reserved reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) reserved reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 <2.5 reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved reserved ns 1,2,3,4, cl = 8 cwl = 5 t ck(avg) reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 <2.5 1.875 <2.5 ns 1,2,3,7 cwl = 7 t ck(avg) 1.5 <1.875 reserved ns 1,2,3,4, cl = 9 cwl = 5,6 t ck(avg) reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 ns 1,2,3,4 cl = 10 cwl = 5,6 t ck(avg) reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 ns 1,2,3 (optional) (optional) ns 5 supported cl settings 5,6,7,8,9 6,8,9 n ck supported cwl settings 5,6,7 5,6,7 n ck
page 48 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 51 ] timing parameters by speed bin speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max clock timing minimum clock cycle time (dll off mode) t ck(dll_off) 8 - 8 - 8 - ns 6 average clock period t ck(avg) see speed bins table ps f clock period t ck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps average high pulse width t ch(avg) 0.47 0.53 0.47 0.53 0.47 0.53 t ck(avg) f average low pulse width t cl(avg) 0.47 0.53 0.47 0.53 0.47 0.53 t ck(avg) f clock period jitter tjit (per) -100 100 -90 90 -80 80 ps clock period jitter during dll locking period tjit (per, lck) -90 90 -80 80 -70 70 ps cycle to cycle period jitter tjit (cc) 200 180 160 ps cycle to cycle period jitte r during dll locking period tjit (cc, lck) 180 160 140 ps cumulative error across 2 cycles t err(2per) - 147 147 - 132 132 - 118 118 ps cumulative error across 3 cycles t err(3per) - 175 175 - 157 157 - 140 140 ps cumulative error across 4 cycles t err(4per) - 194 194 - 175 175 - 155 155 ps cumulative error across 5 cycles t err(5per) - 209 209 - 188 188 - 168 168 ps cumulative error across 6 cycles t err(6per) - 222 222 - 200 200 - 177 177 ps cumulative error across 7 cycles t err(7per) - 232 232 - 209 209 - 186 186 ps cumulative error across 8 cycles t err(8per) - 241 241 - 217 217 - 193 193 ps cumulative error across 9 cycles t err(9per) - 249 249 - 224 224 - 200 200 ps cumulative error across 10 cycles t err(10per) - 257 257 - 231 231 - 205 205 ps cumulative error across 11 cycles t err(11per) - 263 263 - 237 237 - 210 210 ps cumulative error across 12 cycles t err(12per) - 269 269 - 242 242 - 215 215 ps cumulative error across n = 13, 14 ... 49, 50 cycles t err(nper) terr(nper)min = (1 + 0.68ln(n))*tjit(per)min terr(nper)max = (1 = 0.68ln(n))*tjit(per)max absolute clock high pulse width t ch(abs) 0.43 0.43 0.43 t ck(avg) 25 absolute clock low pulse width t cl(abs) 0.43 0.43 0.43 t ck(avg) 26 data timing dqs,dqs to dq skew, per group, per access t dqsq - 200 - 150 - 125 ps 12,13 dq output hold time from dqs, dqs t qh 0.38 - 0.38 - 0.38 - t ck(avg) 12,13 dq low-impedance time from ck, ck t lz(dq) -800 400 -600 300 -500 250 ps 13,14, a dq high-impedance time from ck, ck t hz(dq) - 400 - 300 - 250 ps 13,14, a data setup time to dqs, dqs referenced to vih(ac)vil(ac) levels t ds(base) 75 - 25 - -10 - ps d, 17 data hold time to dqs, dqs referenced to vih(ac)vil(ac) levels t dh(base) 150 - 100 - 65 - ps d, 17 data strobe timing dqs, dqs read preamble t rpre 0.9 - 0.9 - 0.9 - t ck 13, 19, b dqs, dqs differential read postamble t rpst 0.3 note1 0.3 note1 0.3 note1 t ck 11, 13, b dqs, dqs output high time t qsh 0.38 - 0.38 - 0.4 - t ck(avg) 13, b dqs, dqs output low time t qsl 0.38 - 0.38 - 0.4 - t ck(avg) 13, b dqs, dqs write preamble t wpre 0.9 - 0.9 - 0.9 - t ck 1 dqs, dqs write postamble t wpst 0.3 - 0.3 - 0.3 - t ck 1 dqs, dqs rising edge output access time from rising ck, ck t dqsck -400 400 -300 300 -255 255 ps 12,13 dqs, dqs low-impedance time (referenced from rl-1) t lz(dqs) -800 400 -600 300 -500 250 ps 12,13,14 dqs, dqs high-impedance time (referenced from rl+bl/ 2) t hz(dqs) - 400 - 300 - 250 ps 12,13,14 dqs, dqs differential input low pulse width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs, dqs differential input high pulse width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs, dqs rising edge to ck, ck rising edge t dqss -0.25 0.25 -0.25 0.25 -0.25 0.25 t ck(avg) c dqs,dqs faling edge setup time to ck, ck rising edge t dss 0.2 - 0.2 - 0.2 - t ck(avg) c dqs,dqs faling edge hold time to ck, ck rising edge t dsh 0.2 - 0.2 - 0.2 - t ck(avg) c 13.0 timing parameters by speed grade
page 49 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 51 ] timing parameters by speed bin (cont.) speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max command and address timing dll locking time t dllk 512 - 512 - 512 - nck internal read command to precharge command delay t rtp max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - e delay from start of internal write transaction to internal read command t wtr max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - e,18 write recovery time t wr 15 - 15 - 15 - ns e mode register set command cycle time t mrd 4 - 4 - 4 - t ck(avg) mode register set command update delay t mod max (12t ck ,15ns) - max (12t ck ,15ns) - max (12t ck ,15ns) - cas# to cas# command delay t ccd 4 - 4 - 4 - nck auto precharge write recovery + precharge time t dal(min) wr + roundup (t rp / t ck(avg) ) nck multi-purpose register recovery time t mprr 1 - 1 - 1 - nck active to precharge command period t ras 37.5 70,000 37.5 70,000 36 70,000 ns e active to active command period for 1kb page size t rrd max (4t ck ,10ns) - max (4t ck ,7.5ns) - max (4t ck ,6ns) - e active to active command period for 2kb page size t rrd max (4t ck ,10ns) - max (4t ck ,10ns) - max (4t ck ,7.5ns) - e four activate window for 1kb page size t faw 40 - 37.5 - 30 - ns e four activate window for 2kb page size t faw 50 - 50 - 45 - ns e command and address setup time to ck, ck referenced to vih(ac) / vil(ac) levels t is(base) 200 - 125 - 65 - ps b,16 command and address hold time from ck, ck referenced to vih(ac) / vil(ac) levels t ih(base) 275 - 200 - 140 - ps b,16 refresh timing 512mb refresh to refresh or refresh to active command interval t rfc 90 - 90 - 90 - ns 1gb refresh to refresh or refresh to active command interval t rfc 110 - 110 - 110 - ns 2gb refresh to refresh or refresh to active command interval t rfc 160 - 160 - 160 - ns 4gb refresh to refresh or refresh to active command interval t rfc 300 - 300 - 300 - ns 8gb refresh to refresh or refresh to active command interval t rfc 350 - 350 - 350 - ns average periodic refresh interval (0 c tcase 85 c ) t refi 7.8 7.8 7.8 us average periodic refresh interval (85 c tcase 95 c ) t refi 3.9 3.9 3.9 us calibration timing power-up and reset calibration time t zqiniti 512 - 512 - 512 - t ck normal operation full calibration time t zqoper 256 - 256 - 256 - t ck normal operation short calibration time t zqcs 64 - 64 - 64 - t ck 23 reset timing exit reset from cke high to a valid command t xpr max(5t ck , t rfc + 10ns) - max(5t ck , t rfc + 10ns) - max(5t ck , t rfc + 10ns) - self refresh timing exit self refresh to commands not requiring a locked dll t xs max(5t ck ,t rfc + 10ns) - max(5t ck ,t rfc + 10ns) - max(5t ck ,t rfc + 10ns) - exit self refresh to commands requiring a locked dll t xsdll t dllk (min) - t dllk (min) - t dllk (min) - t ck minimum cke low width for self refresh entry to exit timing t ckesr t cke (min) + 1t ck - t cke (min) + 1t ck - t cke (min) + 1t ck - valid clock requirement after self refresh entry (sre) t cksre max(5t ck ,10ns) - max(5t ck ,10ns) - max(5t ck ,10ns) - valid clock requirement before self refresh exit (srx) t cksrx max(5t ck ,10ns) - max(5t ck ,10ns) - max(5t ck ,10ns) -
page 50 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 51 ] timing parameters by speed bin (cont.) speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max power down timing exit power down with dll on to any valid command;exit percharge power down with dll frozen to commands not requiring a locked dll t xp max (3t ck ,7.5ns) - max (3t ck ,7.5ns) - max (3t ck ,6ns) - exit precharge power down with dll frozen to commands requiring a locked dll t xpdll max (10t ck ,24ns) - max (10t ck ,24ns) - max (10t ck ,24ns) - 2 cke minimum pulse width t cke max (3t ck ,7.5ns) - max (3t ck ,5.625ns) - max (3t ck ,5.625ns) - command pass disable delay t cpded 1 - 1 - 1 - nck power down entry to exit timing t pd t cke (min) 9*t refi t cke (min) 9*t refi t cke (min) 9*t refi t ck 15 timing of act command to power down entry t actpden 1 - 1 - 1 - nck 20 timing of pre command to power down entry t prpden 1 - 1 - 1 - nck 20 timing of rd/rda command to power down entry t rdpden rl + 4 +1 - rl + 4 +1 - rl + 4 +1 - timing of wr command to power down entry (bl8otf, bl8mrs, bl4otf) t wrpden wl + 4 +(t wr / t ck ) - wl + 4 +(t wr / t ck ) - wl + 4 +(t wr / t ck ) - nck 9 timing of wra command to power down entry (bl8otf, bl8mrs, bl4otf) t wrapden wl + 4 +wr +1 - wl + 4 +wr +1 - wl + 4 +wr +1 - nck 10 timing of wr command to power down entry (bl4mrs) t wrpden wl + 2 +(t wr / t ck ) - wl + 2 +(t wr / t ck ) - wl + 2 +(t wr / t ck ) - nck 9 timing of wra command to power down entry (bl4mrs) t wrapden wl +2 +wr +1 - wl +2 +wr +1 - wl +2 +wr +1 - nck 10 timing of ref command to power down entry t refpden 1 - 1 - 1 - 20,21 timing of mrs command to power down entry t mrspden t mod(min) - t mod(min) - t mod(min) - t ck odt timing odt high time without write command or with wirte com- mand and bc4 odth4 4 - 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - 6 - nck asynchronous rtt tum-on delay (power-down with dll frozen) t aonpd 1 9 1 9 1 9 ns asynchronous rtt tum-off delay (power-down with dll frozen) t aofpd 1 9 1 9 1 9 ns odt turn-on t aon -400 400 -300 30 -250 250 ps 7,12 rtt_nom and rtt_wr turn-off time from odtloff refer- ence t aof 0.3 0.7 0.3 0.7 0.3 0.7 t ck(avg) 8,12 rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 0.3 0.7 t ck(avg) 12 write leveling timing first dqs pulse rising edge after tdqss margining mode is programmed t wlmrd 40 - 40 - 40 - t ck 3 dqs/dqs delay after tdqs margining mode is programmed t wldqsen 25 - 25 - 25 - t ck 3 setup time for tdqss latch t wls 325 - 245 - 195 - ps hold time of tdqss latch t wlh 325 - 245 - 195 - ps write leveling output delay t wlo 0 9 0 9 0 9 ns write leveling output error t wloe 0 2 0 2 0 2 ns
page 51 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c jitter notes specific note a when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(mper),act of the inp ut clock, where 2 <= m <= 12. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdram has terr(mper),act,min = - 172 ps and terr(mper),act,max = + 193 ps, then tdqsck,min(derated) = tdqsck,min - terr(mper),act,max = - 400 ps - 193 ps = - 593 ps and tdqsck,max(derated) = tdqsck,max - terr(mper),act,min = 400 ps + 172 ps = + 572 ps. similarly, tlz(dq) for ddr3-800 derates to tlz(dq),min(derated) = - 800 ps - 1 93 ps = - 993 ps and tlz(dq),max(derated) = 400 ps + 172 ps = + 572 ps. (caution on the min/max usage!) note that terr(mper),act,min is the minimum measured value of terr(nper) where 2 <= n <= 12, and terr(mper),act,max is the maxi mum measured value of terr(nper) where 2 <= n <= 12 specific note b when the device is operated with input clock jitter, this paramet er needs to be derated by the actual tjit(per),act of the inpu t clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdram has tc k(avg),act = 2500 ps, tjit(per),act,min = - 72 ps and tjit(per) ,act,max = + 93 ps, then trpre,min(derated) = trpre,min + tjit(per),act,min = 0.9 x tck( avg),act + tjit(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps . similarly, tqh,min(der- ated) = tqh,min + tjit(per),act, min = 0.38 x tck(avg),act + tjit(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (caution on the min/max usage!) specific note c these parameters are measured from a data strobe signal (dqs(l/u), dqs (l/u)) crossing to its respec tive clock signal (ck, ck ) crossing. the spec val- ues are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), et c.), as these are relative to the clock signal crossing. that is, these parameters should be met w hether clock jitter is present or not. specific note d these parameters are measured from a data signal (dm(l/u), dq(l /u)0, dq(l/u)1, etc.) transition edge to its respective data str obe signal (dqs(l/u), dqs (l/u)) crossing. specific note e for these parameters, the ddr3 sdram device s upports tnparam [nck] = ru{ tparam [ns] / tc k(avg) [ns] }, which is in clock cycle s, assuming all input clock jitter specifications are satisfied. for example, the device will support tnrp = ru{trp / tck(avg)}, which is in clock cycles, if all i nput clock jitter specificat ions are met. this means: for ddr3-800 6-6-6, of which trp = 15ns, the devic e will support tnrp = ru{trp / tck(avg)} = 6, as long as the input clock jitter s pecifications are met, i.e. precharge command at tm and active command at tm+6 is valid ev en if (tm+6 - tm) is less than 15ns due to input clock jitter.
page 52 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c timing parameter notes 1. actual value dependant upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: re ad (and rap) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register 5. value must be rounded-up to next higher integer value 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. for definition of rtt turn-on time taon see "device operation" 8. for definition of rtt turn-off time taof see "device operation". 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles as programmed in mr0 11. the maximum postamble is bound by thzdqs(max) 12. output timing deratings are relative to the sdram input cloc k. when the device is operated wi th input clock jitter, this pa rameter needs to be derated by tbd 13. value is only valid for ron34 14. single ended signal parameter. refer to chapter for definition and measurement method. 15. trefi depends on toper 16. tis(base) and tih(base) values are for 1v/n s cmd/add single-ended slew rate and 2v/ns ck, ck differential slew rate, note for dq and dm signals, vref(dc) = vrefdq(dc). for input onl y pins except reset, vref(dc)=vrefca(dc). see "address/ command setup, hold and derating" on page 53. 17. tds(base) and tdh(base) values are for 1v/n s dq single-ended slew rate and 2v/ns dqs, dqs differential slew rate. note for dq and dm signals, vref(dc)= vrefdq(dc). for input only pins except reset , vref(dc)=vrefca(dc). see "data setup, hold and slew rate derating" on page 59. 18. start of internal write transaction is definited as follows ; for bl8 (fixed by mrs and on-the-fly) : rising clock edge 4 clock cycles after wl. for bc4 (on-the-fly) : ri sing clock edge 4 cloc k cycles after wl for bc4 (fixed by mrs) : ri sing clock edge 2 clo ck cycles after wl 19. the maximum preamble is bound by tlzdqs(max) 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in pro gress, but power-down idd spec will not be appli ed until finishing those operations. 21. altough cke is allowed to be registered low after a refresh co mmand once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. see "device operation". 22. defined between end of mpr read burst and mrs which reloads mpr or di sables mpr function. 23. one zqcs command can effectively correct a minimum of 0.5 % (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maxi-mum sensitivit ies specified in the ?output driver voltage and te mperature sensitivity? and ?odt voltage and t emperature sensitivity? tables. the appropriate interval between zq cs commands can be determined from these t ables and other applicationspecific one me thod for calculating the interval between zqcs commands, given t he temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is s ubject to in the applica- tion, is illustrated. the interval co uld be defined by the following formula: where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) for example, if tsens = 1.5% / c , vsens = 0.15% / mv, tdriftrate = 1 c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calculated as: 24. n = from 13 cycles to 50 cycles . this row defines 38 parameters. 25. tch(abs) is the absolute instantaneous cl ock high pulse width, as measured from one rising edge to the following falling ed ge. 26. tcl(abs) is the absolute instantaneous clock low pulse widt h, as measured from one falling edge to the following rising edg e. 27. the tis(base) ac150 specifications are adjusted from the tis(base) specification by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mv and another 25 ps to account for the earlier reference point [(175 mv - 150 mv) / 1 v/ns]. zqcorrection (tsens x tdriftrate) + (vsens x vdriftrate) 0.5 (1.5 x 1) + (0.15 x 15) = 0.133 ~ ~ 128ms
page 53 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c address / command setup, hold and derating: for all input signals the total tis (setup time) and tih (hold time ) required is calculated by adding the data sheet tis(base) and tih(base) value (see table 53) to the ? tis and ? tih derating value (see table 54) respectively. example: tis (total setup time) = tis(base) + ? tis setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tis ) nominal slew rate for a fa lling signal is defined as the slew rate between the last crossing of vref(dc) and the firs t crossing of vil(ac)max. if the actual signal is always earlie r than the nominal slew rate line between shaded ?vref(dc) to ac region?, use nominal slew rate for derating value (see figure 23). if the actual signal is later than the nominal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac lev el to dc level is used for derating value (see figure 25). hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the fi rst crossing of vref(dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc to vref (dc) region?, use nominal slew rate for derating value (see figure 24). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value (see figure 26). for a valid transition the input signal has to remain above/ below vih/il(ac) for some time tvac (see table 55). although for slow slew rates the total setup time might be negat ive (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in table 54 , the derating values may obt ained by linear interpolation. these values are typicall y not subject to production test. they ar e verified by design and characterization. [ table 53 ] add/cmd setup and hold base-values for 1v/ns note : ac/dc referenced for 1v/ns dq-slew rate and 2v/ns dqs slew rate note : the tis(base)-ac150 specifications are further adjusted to add an addi-tional 100ps of derating to accommodate for the lower alternate thresh-old of 150mv and another 25ps to acccount for the earlier reference point [(175mv-150mv)/1 v/ns]. [ps] ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 reference tis(base) 200 125 65 tbd v ih/l(ac) tih(base) 275 200 140 tbd v ih/l(dc) tis(base)-ac150 - - 65+125 tbd+125 v ih/l(ac) [ table 54 ] derating values ddr3-800/1066 tis/tih-ac/dc based ? tis, ? tih derating [ps] ac/dc based ac175 threshold -> vih(ac) = vref(dc) + 175mv, vil(ac) = vref(dc) - 175mv clk,clk differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih cmd/ add slew rate v/ns 2.08850885088509658104661127412084128100 1.559345934593467427550835891689974 1.0000000881616242432344050 0.9-2 -4 -2 -4 -2 -4 6 4 1412202030303846 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 13 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 6 10 0.4 -62 -60 -62 -60 -60 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10
page 54 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c [ table 55 ] derating values ddr3-1333/1600 tis/tih-ac/dc based - alternate ac150 threshold [ table 56 ] required time t vac above vih(ac) {blow vil(ac)} for valid transition ? tis, ? tih derating [ps] ac/dc based alternate ac150 threshold -> vih(ac) = vref(dc) + 150mv, vil(ac) = vref(dc) - 150mv clk,clk differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih cmd/ add slew rate v/ns 2.070507550755083589166997410784115100 1.550345034503458426650745882689084 1.0000000881616242432344050 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 -10 0 -10 0 -10 8 -2 16 6 241432244040 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 slew rate[v/ns] t vac @175mv [ps] t vac @50mv [ps] min max min max >2.0 75 - 175 - 2.0 57 -170 - 1.5 50 - 167 - 1.0 38 -163 - 0.9 34 - 162 - 0.8 29 -161 - 0.7 22 - 159 - 0.6 13 -155 - 0.5 0 - 150 - < 0.5 0 -150 -
page 55 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c v ss ck ck tds tdh setup slew rate setup slew rate rising signal falling signal delta tf delta tr v ref(dc) - vil(ac)max delta tf = vih(ac)min - v ref(dc) delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate vref to ac region vref to ac region figure 21 - illustration of nominal sl ew rate and tvac for setup time tds (fo r dq with respect to strobe) and tis (for add/cmd with resp ect to clock). tis tih tds tdh tis tih tvac tvac note :clock and strobe are drawn on a different time scale. dqs dqs
page 56 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c v ss ck ck hold slew rate hold slew rate falling signal rising signal delta tr delta tf v ref(dc) - vil(dc)max delta tr = vih(dc)min - v ref(dc) delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region figure 22 - illustration of nominal slew rate for hold time tdh (for dq with resp ect to strobe) and tih (for add/cmd with respect to clock). tis tih tis tih dc to v ref region note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs
page 57 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c v ss setup slew rate setup slew rate rising signal falling signal delta tf delta tr tangent line[v ref(dc) - vil(ac)max] delta tf = tangent line[vih(ac)min - v ref(dc) ] delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line figure 23. illustration of tangent line for setup time tds (for dq with re spect to strobe) and tis (for add/cmd with respect to clock) ck ck tis tih tis tih tvac note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs
page 58 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c v ss hold slew rate delta tf delta tr tangent line [ vih(dc)min - v ref(dc) ] delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] delta tr = rising signal figure 24 - illustration of tangent line for hold time tdh (for dq with re spect to strobe) and tih (for add/cmd with respect to clock) ck ck tis tih tis tih note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs
page 59 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c data setup, hold a nd slew rate derating: for all input signals the total tds (setup time) and tdh (hold ti me) required is calculated by adding the data sheet tds(base) and tdh(base) value (see table 57) to the ? tds and ? tdh (see table 58) derating value respectively. ex ample: tds (total setup time) = tds(base) + ? tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the fir st crossing of vih(ac)min. setup (tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the fi rst crossing of vil(ac)max (see figure 27). if the actual signal is always earlier than the nominal slew ra te line between shaded ?vref(dc) to ac region?, use nominal slew rate for derating value. if the actual signal is late r than the nominal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is u sed for derating value (see figure 29). hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the fi rst crossing of vref(dc). hold (tdh) nominal slew rate for a fallin g signal is defined as the slew rate between the last crossing of vih(dc)min and the f irst crossing of vref(dc) (see figure 28). if the actual signal is al ways later than the nominal slew rate line between shaded ?dc level to vref(dc) regi on?, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region? , the slew rate of a tangent line to the actual signal from the dc level to vref(d c) level is used for derating value (see figure 30). for a valid transition the input signal has to remain abov e/below vih/il(ac) for some time tvac (see table 59). although for slow slew rates the total setup time might be negativ e (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete t he transition and reach vih/il(ac). for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subj ect to production test. they are ve rified by design and characterization [ table 57 ] data setup and hold base-value note : ac/dc referenced for 1v/ns dq-slew rate and 2 v/ns dqs slew rate) [ table 58 ] derating values ddr3-800/1066 tis/tih-ac/dc based note : a. cell contents shaded in red are defined as ?not supported?. [ table 59 ] required time t vac above vih(ac) {blow vil(ac)} for valid transition [ps] ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 reference tds(base) 75 25 -10 tbd v ih/l(ac) tdh(base) 150 100 65 tbd v ih/l(dc) ? tds, ? tdh derating [ps] ac/dc based a dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh dq slew rate v/ns 2.0885088508850---------- 1.55934593459346745-------- 1.0000000881616 ------ 0.9---2-4-2-46414122220---- 0.8-----6-102-210618142624-- 0.7-------3-85013821182934 0.6---------1-107-21582324 0.5-----------11-16-2-6610 0.4-------------30-26-22-10 slew rate[v/ns] t vac [ps] min max >2.0 75 - 2.0 57 - 1.5 50 - 1.0 38 - 0.9 34 - 0.8 29 - 0.7 22 - 0.6 13 - 0.5 0 - <0.5 0 -
page 60 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c v ss ck ck tds tdh setup slew rate setup slew rate rising signal falling signal delta tf delta tr v ref(dc) - vil(ac)max delta tf = vih(ac)min - v ref(dc) delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate vref to ac region vref to ac region figure 27 - illustration of nominal sl ew rate and tvac for setup time tds (fo r dq with respect to strobe) and tis (for add/cmd with resp ect to clock). tis tih tds tdh tis tih tvac tvac note :clock and strobe are drawn on a different time scale. dqs dqs
page 61 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c v ss ck ck hold slew rate hold slew rate falling signal rising signal delta tr delta tf v ref(dc) - vil(dc)max delta tr = vih(dc)min - v ref(dc) delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region figure 28 - illustration of nominal slew rate for hold time tdh (for dq with resp ect to strobe) and tih (for add/cmd with respect to clock). tis tih tis tih dc to v ref region note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs
page 62 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c v ss setup slew rate setup slew rate rising signal falling signal delta tf delta tr tangent line[v ref(dc) - vil(ac)max] delta tf = tangent line[vih(ac)min - v ref(dc) ] delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line figure 29 - illustration of tangent line for setup time tds (for dq with re spect to strobe) and tis (for add/cmd with respect to clock) ck ck tis tih tis tih tvac note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs
page 63 of 63 rev. 1.0 june 2007 1gb ddr3 sdram k4b1g04(08/16)46c v ss hold slew rate delta tf delta tr tangent line [ vih(dc)min - v ref(dc) ] delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] delta tr = rising signal figure 30 - illustration of tangent line for hold time tdh (for dq with re spect to strobe) and tih (for add/cmd with respect to clock) ck ck tis tih tis tih note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs

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